Difference between revisions of "Nanometer (nm)"
Jump to navigation
Jump to search
Tags: Mobile web edit, Mobile edit |
|||
| Line 13: | Line 13: | ||
* 7 nm [[POWER10]] (2020), [[D1]] | * 7 nm [[POWER10]] (2020), [[D1]] | ||
* 5 nm [[A14]], [[A15]], [[Apple M1]] (2020) ([[Samsung]], [[TSMC]]), [[Apple M2]] (June 2022) | * 5 nm [[A14]], [[A15]], [[Apple M1]] (2020) ([[Samsung]], [[TSMC]]), [[Apple M2]] (June 2022) | ||
| + | * 3 nm [[Apple M3]] | ||
* 2 nm https://www.anandtech.com/show/16656/ibm-creates-first-2nm-chip | * 2 nm https://www.anandtech.com/show/16656/ibm-creates-first-2nm-chip | ||
Latest revision as of 10:13, 30 December 2023
- 250 nm
- 180 nm
- 130 nm
- 90 nm
- 65 nm
- 45 nm
- 32 nm
- 22 nm
- 14 nm Comet Lake, POWER9, Intel Xenon Silver, FSD Chip
- 10 nm Ice Lake
- 7 nm POWER10 (2020), D1
- 5 nm A14, A15, Apple M1 (2020) (Samsung, TSMC), Apple M2 (June 2022)
- 3 nm Apple M3
- 2 nm https://www.anandtech.com/show/16656/ibm-creates-first-2nm-chip
See also[edit]
- Intel, AMD, POWER, ARM, core, thread
- nm
- CPU, GPU, NPU, TPU, DPU, Groq, Proliant, thread (
Pthreads), processor, CPU socket, core, ARM , CPU Virtualization, Intel, AMD,nm,lscpu, AVX-512, Passthrough, CPU intensive, Graviton processor, Branch predictor, vCPU, SSE, Power - Silicon, SMIC, Intel, TSMC, ASM, ASML, Alusil
Advertising:
